Computer designers are always searching for faster memory devices that will allow them to design faster computers. A significant limitation on a computer's operating speed is the time required to transfer data between a processor and a memory circuit under a read or write data transfer. Memory circuits, such as dynamic random access memories ("DRAMs"), usually include a large number of memory cells arranged in one or more arrays, each having rows and columns. The memory cells provide locations at which the processor can store and retrieve data. The more quickly the processor can access the data within the memory cells, the more quickly it can perform a calculation or execute a program using the data.
FIG. 1 shows, in part, a typical computer architecture. A central processing unit ("CPU") or processor 50 is connected to a bus system 52, which in turn is connected to a system or memory controller 54. The processor 50 can also be connected, through the bus system 52, to a datapath integrated circuit ("IC") 56. The memory controller 54 and the datapath IC 56 serve as interface circuitry between the processor 50 and a memory device 60. Although the datapath IC 56 and the memory device 60 are shown as separate integrated circuits, it will be understood that the circuitry of the datapath IC can be integrated into the memory device. The processor issues a command C and an address A which are received and translated by the memory controller 54, which in turn applies command signals and an address to the memory device 60. Corresponding to the processor-issued commands C and addresses A, data D is transferred between the processor 50 and the memory device 60 via the datapath IC 56.
FIG. 2 illustrates a type of memory device 60 currently used, namely a synchronous dynamic random access memory ("SDRAM"), or its close relative, a synchronous graphics random access memory ("SGRAM") circuit 100. A main difference between the SDRAM and the SGRAM is the division of the memory therein. For example, the SGRAM has a double word width, i.e., it can access 32 bits in parallel for each address. The memory device 200 includes as its central memory element two memory array banks 101A, 101B, which operate under the control of a control logic circuit 102. Each of the memory arrays 101A, B includes a plurality of memory cells (not shown) arranged in rows and columns. For purposes of discussion, the memory device 200 has an 8-bit word width--meaning that for each specified memory address (combined bank, row and column address) there is a one-to-one correspondence with 8 memory cells in one of the arrays 101A, B. The processor 50 (see FIG. 1) also preferably operates on data elements of 8 bits each.
A system clock (not shown) provides a clock signal CLK to the control circuit 102 of the memory device 200, as well as to the processor 50 and controller 54 (FIG. 1) accessing the memory device. However, the signal CLK must be precisely registered with other input signals, such as control signals described below, that are applied to the memory device 200 so that those input signals will be available to the memory device when the memory device 200 attempts to operate on those input signals. However, it is sometimes difficult to ensure that the CLK signal is precisely registered to the other input signals, particularly as clock frequencies increase at higher operating speeds. Moreover, the signal CLK may be corrupted by noise or transient signals that can adversely affect the operation of the memory device 200, and, in some cases, the duration of the CLK signal may be too short for the proper operation of the memory device 200. Precise registration of the CLK signal with other signals, as well as noise and other transients, are some of the problems that adversely affect the operation of conventional memory devices 60 and limit their operating speeds.
Command signals input to the control circuit 102 are decoded by command decode circuitry 104. These signals are well known in the art, and include signals such as row address strobe (RAS), column address strobe (CAS) and write enable (WE). (The line or bar over, or an "*" following, the acronym for a signal generally indicates that the active state for the particular signal is a logical low value.)
Distinct combinations of the various command signals constitute distinct commands. For example, the combination of RAS low, CAS high and WE low can represent a PRECHARGE command. Examples of other well known commands include ACTIVE, READ, WRITE and NOP. Responding to the applied command, the control circuit 102 sends control signals on control lines 103A-H to other parts of the memory device 200, controlling the timing and access to the memory cells in arrays 101A, 101B.
In operation, an address is input to an address register 106, indicating the memory location to be accessed. The address specifies one of the memory banks 101A, B and a row and column address within the specified bank. The address register 106 provides the address information to the control circuit 102, and to a row-address multiplexer 107 and a column-address latch and decode circuit 110. The row-address multiplexer 107 multiplexes the row address information and provides it to one row-address latch and decode circuit 108A or 108B corresponding to the one of the memory banks 101A, B to be accessed, respectively. Each of the row latch and decode circuits 108A, 108B takes a row address provided by the row-address multiplexer 107 and activates a selected row of memory cells (not shown) in the memory array 101A, 101B by selecting one of several row access lines 112A, 112B, all respectively. The column latch and decode circuit 110 takes a column address provided by the address register 106 and selects one of several column access lines 114A, 114B, each of which is coupled to one of the memory arrays 101A, 101B by an I/O interface circuit 116A, 116B, all respectively. Each of the I/O interface circuits 116A, 116B selects the memory cell(s) corresponding to the column location in an activated row. The I/O interface circuits 116 include sense amplifiers which determine and amplify the logic state of the selected memory cells, and I/O gating of data to and from a data I/O register 118. The data register 118 is connected to a data bus which is used to input and output data to and from the memory device 200 over DQ lines.
Data transfer cycles typically involve several steps and each step takes time. For example, a read access requires the control circuit 102 of the memory device 200 to decode certain commands and a memory address. The control circuit 102 must then provide control signals to the circuitry accessing the memory array banks 101A, 101B in order to activate the selected row in the selected memory bank, allow time for sense amplifiers to develop signals from the selected column in the memory bank, transfer data from these sense amplifiers to the data register 118 where the data is then made available on the data bus, and terminate the cycle by precharging the row for subsequent access. Steps that are particularly time consuming include the activation step and the precharge step which can result in a substantial read latency (the time between registration in the memory device of a read command and the availability of the accessed data on the data bus).
Other steps during data transfer cycles also require significant amounts of time. For example, a memory device having a sequential or "burst" mode for generating serial addresses requires a finite amount of time for initiating the burst mode, and thereafter sequentially generating the subsequent addresses. U.S. Pat. No. 5,452,261 describes a possible solution to this delay by employing a serial or burst address generator that first receives an externally generated start address, and thereafter generates subsequent addresses as clock signals arrive to the generator. The address generator is preset to the second address in the sequence following the start address and simultaneously the start address is connected by an external address enable switch to an output terminal of the address generator, thereby bypassing the address sequencer.
As mentioned above, input command signals input to the memory device 200 are initially buffered in the control circuit 102, and then decoded into internal control signals. The buffering of the input command signals necessarily delays the decoding and ultimate application of the internal command signals to their appropriate circuitry. If two or more input command signals must be decoded and applied to control certain downstream circuits, the circuits must wait until all of the signals have been decoded and received by the downstream circuits before they can be appropriately controlled. While these delays in waiting for receipt of the appropriate signals have been acceptable in prior devices, as the speed of memory devices increases, they will soon be unable to quickly and effectively operate the device with such delays.
U.S. Pat. No. 5,493,530 provides a possible solution to this problem by describing a synchronous memory device with input registers associated with the memory array input lines, where logic gates are associated with the registers. The logic gates are located upstream of the registers between the input terminals of the device and the registers. Hence, the logic gates not only provide a needed logic function, but also provide necessary delays to meet the specified hold time delay in synchronous circuits.
The command and address signals supplied to the memory device 200 are initially buffered by being input to registers in the control circuit 102. The registers output high or active signals only after being clocked. If significant downstream circuitry exists following the register, but before the circuitry that is controlled by the active signal, the active signal is delayed by all of the downstream circuitry after the signal is output from the register. Such delays can affect the performance of high speed memory devices.
In most synchronous memory devices such as the memory device 200, signals input to the device have a specified period in which to be read in before the clock transitions, and a period in which to be recognized after the clock transitions, typically known as the set-up and hold times, respectively. At times, a signal applied to the device, such as an address, may not arrive at the address register 106 until just a few nanoseconds before the clock transitions, i.e., before the set-up time. As a result, this address is not recognized and registered by the device and thus is lost. As a result, the set-up and hold times must be increased, or the speed of the clock decreased, to insure that such signals are appropriately registered by the device. Such solutions, however, necessarily decrease the speed of the device, which is obviously undesirable.
Another limitation of conventional SDRAM and SGRAM devices results from their physical layouts. During the design of memory devices such as the memory device 200, one memory array bank is initially designed, and thereafter, the second array bank is simply created as a mirror image of the first array bank. Therefore, the SGRAM device is considerably easier to design since only one array bank needs to be designed. However, arrangements of all memory cells, data I/O paths, row and column decoders, etc. are duplicated, even though some of such circuitry is redundant. This circuitry not only increases the complexity of the SGRAM, but requires additional area on the die. As circuit density of semiconductor memory devices increases, this additional area leads to wasted area that could otherwise be used for additional circuitry.
The memory array banks 101A, 101B of the memory device 200 are typically centrally located on the die. Data or DQ pads, which are coupled to the memory array banks, are then positioned at the periphery of the two array banks, along the two edges that extend perpendicularly to the ends of the rows for each array bank. Multiple I/O lines extend between columns of memory cells and one of the data lines that ultimately are coupled to the appropriate DQ0-DQ31 pad. These multiple I/O lines require additional area on the die, even though, at any given time, only one of the I/O lines is ever coupled to the one data line. Since each sub-array of memory cells requires multiple I/O lines, the cost in die area can be significant.
An additional detriment to the layout of typical memory devices is the time required to route data from a column to a DQ pad. It takes a finite amount of time for the data to travel to and from the pads on the memory device to the respective columns of memory cells, particularly if the pads are located far from a given memory cell. Moreover, if one DQ pad is located close to its respective sub-array, while another pad is located much further from its corresponding sub-array, the different data paths necessarily lead to different propagation delays. As the speed of memory devices increases, these propagation delays can be significant, possibly leading to errors.
The column address latch and decode circuit 110 of the prior art memory device 200 include a redundant column compare circuit. As is conventional with memory devices such as DRAM's, the memory arrays 101 of the memory device 200 includes extra columns of memory cells (known as redundant columns) that can be used to replace defective columns of memory cells. A redundant column is selected for use when an unsuccessful attempt is made to write data to or read data from a defective column. For this reason, before data can be written to or read from the memory array at a specific address, a comparison must be made between that address and a record of addresses for defective columns. If the column being addressed is found to be defective, then the redundant column is used in place of the addressed column.
The use of redundant columns results in significant improvement in the yield of the semiconductor fabrication processes because it would otherwise be necessary to discard the memory device 200 if any of its columns were defective. Similar improvements in the yield of the semiconductor fabrication processes also result from providing redundant rows to replace defective rows. These redundant rows are selected in basically the same manner that redundant columns are selected, as explained above. Although the use of redundant rows and columns can significantly improve memory device yields, it can also significantly slow the operating speed of memory devices. The primary problem is the need to compare addresses to the addresses of defective rows and columns before a row and column can be addressed. The time it takes to accomplish this comparison correspondingly increases the time required to complete a write or read operation, even if there is no need to use a redundant row or column.
The delay caused by checking column redundancy is exacerbated by the availability of addresses from more than one source. In particular, addresses in some memory devices, such as SGRAMs, can be internally generated. Of course, the addresses can also be generated externally, such as in a controller 54, in a conventional manner. In such cases, it has been necessary to first determine whether a write or a read operation will be to either an internally generated or externally generated address. Once, that determination has been made, the memory device can determine whether the selected address corresponds to a defective row or column, and, if so, select a redundant row or column. Only then can the memory device write to or read from the memory array at the intersection of the selected row and column. These operations can significantly delay the operating speed of memory devices.
Another factor in slowing the operating speed of conventional memory devices stems from performing certain operations in the same manner for both write and read operations, even though more time is required for a read operation. Specifically, during a write or a read operation, prior art memory devices pull-up I/O lines prior to applying data to the I/O lines from either digit lines of the memory array or to a data write driver of the data path circuitry. In these prior art memory devices, the I/O lines are pulled-up for the same duration in a read operation, in which data is transferred to the I/O lines, and transferred from the digit lines of the array to a write operation, in which data is transferred from the data write driver to the I/O lines. Yet the required pull-up time can be shorter for a write operation, thus wasting time during a write operation and unnecessarily slowing the operation of the memory device.
Yet another factor that slows memory device performance involves the Vccp pump, which provides a voltage greater than the supply voltage Vcc. The Vccp pump provides a high voltage to charge both the row lines and the data output lines. The Vccp pump necessarily requires a certain amount of time to perform both operations. Therefore, the Vccp pump thus cannot charge and boost both the row lines and the data output lines simultaneously.
Overall, it is desirable to decrease the time required to perform data transfer cycles in memory devices, to thereby meet the demand for faster memory devices in the market place. Therefore, it is desirable to reduce the above-described and other delays that occur during data transfer cycles and generally improve the performance of memory devices.